Transconductance amplifiers are used for converting an input voltage into an output current.
Many applications require a transconductance amplifier that has linear transfer characteristics and operates over a wide bandwidth.
One solution, shown in FIG. 1, shows a transconductance amplifier 100 having a first input circuit 101, a second input circuit 102, a first output circuit 103 and a second output circuit 104, with the first input circuit 101 and the second input circuit 102 being coupled via a resistor 105.
The first input circuit 101 has a first P-type FET 106 that has its source coupled to a first current source 107, which in turn is coupled to a supply line VDD, and its drain coupled to a second current source 108, which in turn is coupled to a reference line GND, for example ground. The gate of the P-type FET 106 acts as the input Vin1 for the first input circuit 101. Additionally, the input circuit 101 includes a first N-type FET 109 in which the source is coupled to the reference line GND, the gate is coupled to a point between the first P-type FET drain and the second current source 108, and the drain is coupled to a point between the P-type FET source and the first current source 107 to form a feedback loop. The drain of the first N-type FET 109 is additionally coupled to a first interface of the resistor 105.
The second input circuit 102 is of similar design to the first input circuit 101 having a second P-type FET 110 that has its source coupled to a third current source 111, which in turn is coupled to the supply line VDD, and its drain coupled to a fourth current source 112, which in turn is coupled to the reference line GND, for example ground. The gate of the P-type FET 110 acts as the input Vin2 for the second input circuit 102. Additionally, the second input circuit 102 includes a second N-type FET 113 in which the source is coupled to the reference line GND, the gate is coupled to a point between the second P-type FET drain and the fourth current source 112, and the drain is coupled to a point between the second P-type FET source and the third current source 111 to form a feedback loop. The drain of the second N-type FET 113 is additionally coupled to a second interface of the resistor 105.
The first output circuit 103 has a third N-type FET 114 that is arranged to form a current mirror with the feedback loop formed by the first N-type FET 109 where the third N-type FET 114 has its source coupled to the reference line GND, its drain couple to a fifth current source 115, which in turn is couple to the supply line VDD, and its gate is coupled to a point between the drain of the first P-type FET 106 and the second current source 108. The output Iout1 for the first output circuit 103 is formed at a point between the drain of the third N-type FET 114 and the fifth current source 115.
The second output circuit 104 is of similar design to the first output circuit 103 having a fourth N-type FET 116 that is arranged to form a current mirror with the feedback loop formed by the second N-type FET 113 where the fourth N-type FET 116 has its source coupled to the reference line GND, its drain couple to a sixth current source 117, which in turn is couple to the supply line VDD, and its gate is coupled to a point between the drain of the second P-type FET 110 and the fourth current source 112. The output Iout2 for the second output circuit 104 is formed at a point between the drain of the fourth N-type FET 116 and the sixth current source 117.
In order to obtain a linear voltage to current transfer function the voltage across the resistor 105 should be kept equal to the input voltage difference (i.e. Vin1−Vin2). This is achieved by keeping the drain-source current of the first P-type FET 106 and the second P-type FET 110 constant by means of the feedback loops formed by the first N-type FET 109 and the second N-type FET 113 respectively. The feedback loops compensates for current diverted from the first current source 107 and third current source 111 through the resistor 105, thereby ensuring that the drain-source current of the first P-type FET 106 and the second P-type FET 110 is maintained.
As the third N-type FET 114 and fourth N-type FET 116 form current mirrors with the feedback loops their drain-source current will be identical to that for the first N-type FET 109 and second N-type FET 113 respectively, which forms the transconductance amplifier output current Iout1, Iout2.
By way of illustration, when the input voltage difference is zero (i.e. Vin1−Vin2=0) no current will flow through the resistor 105 and consequently the current that flows through the first N-type FET 109 and the second N-type FET 113 is identical to the current flow in the output circuits and consequently there will be no output current.
When the input voltage difference is positive (i.e. Vin1−Vin2>0) a current (i.e. Vin1−Vin2/R) will flow into the resistor 105 and increase the current in the second N-type FET 113 by the same amount. This current is copied by the second N-type FET/fourth N-type FET current mirror arrangement into the fourth N-type FET 116 to provide an output current in the second output circuit 104 that is equal to (Vin1Vin2)/R.
Correspondingly, when the output current in the second output circuit 104 is equal to (Vin1−Vin2)/R the current flowing into the first N-type FET 109 is reduced by (Vin1−Vin2)/R and this reduced current is copied into the third N-type FET 114 to provide an output current in the first output circuit 103 that is equal to −(Vin1−Vin2)/R.
As the output current from the first output circuit 103 equals the negative of the second output circuit 104 the transconductance of the transconductance amplifier 100 is given by 1/R.
However, even though current mirrors are well suited for mirroring fixed currents they are not so suitable for mirroring variable currents. Consequently, the use of a current mirror to generate the transconductance amplifier's output current can limit the linearity of the voltage to current transfer function.
It is desirable to improve this situation.